Pin details of 8085

• Pin Description

The following describes the function of each pin:

• A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.

• AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes.

• ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated.

• SO, S1 (Output)

Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.

• RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer.

• WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

• READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.

• HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

• HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

• INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

• INTA (Output)

INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5

• RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.

• TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

• RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied.

• RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.

• X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency.

• CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.

• IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes.

• SID (Input)

Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

• SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

• Vcc

+5 volt supply.

• Vss

Ground Reference.

Flag Register Of 8085

Pin-out diagram of 8085

Interrupts in 8085

The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):

INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:

• One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
• CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.

RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address.

RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address.

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

Intel 8085 microprocessor & Architecture

• The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977 
• Max. CPU clock rate 3, 5 and 6 MHz 
• The "5" in the model number came from the fact that the 8085 requires only a +5-volt (V) power supply 
• The 8085 is a conventional von Neumann design based on the Intel 8080 
• It has 8-bit data bus & 16-bit address bus 
• The 8-bit data bus was instead multiplexed with the lower part of the 16-bit address bus to limit the number of pins to 40 
• The 8085 has extensions to support new interrupts, with three maskable interrupts (RST 7.5, RST 6.5 and RST 5.5) 

Instruction set of 8080

8080 instruction set consists of the following instructions:

• Data moving instructions.
• Arithmetic - add, subtract, increment and decrement.
• Logic - AND, OR, XOR and rotate.
• Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts.
• Input/Output instructions.
• Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

REGISTER ORGANISATION OF 8080

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.

Flag is an 8-bit register containing 5 1-bit flags:

• Sign - set if the most significant bit of the result is set.
• Zero - set if the result is zero.
• Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.
• Parity - set if the parity (the number of set bits in the result) is even.
• Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:

• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.

Program counter is a 16-bit register.

Intel-8080 Microprocessor & Architecture

• It is a 8-bit microprocessor
• Max. clock frequency 2 to 4-MHz
• 64 Kb RAM 
• It has 40-pin DIP Ic
• It has sometimes labeled "The 1st truly usable microprocessor"
• It has 16-bit address bus & 8-bit data bus
• The processor had seven 8-bit registers (A,B,C,D,E,H & L)
• Reg A has 8-bit accumulator & other 6 reg could be used as three 16-bit register pair (BC,DE,HL)
• It also had a 16-bit stack pointer to memory & 16-bit program counter

Intel-8008 Microprocessor & Architecture

• It is the 1st 8-bit microprocessor
• Max. clock frequncy : 800khz
• 16 Kb memory
• 7-level deep stack
• 8 Input / 24 output ports
• 18 pin DIP IC
• 14 bit address bus
• Applications : Dumb terminals,general calculations,botting machines

ARCHITECTURE OF INTEL 4004

• The i-4004 is a 4-bit mp
• It has 4-bit ALU
• It can process 4-bit data at a time
• Internal subroutine stack 3 level deep

INTEL 4004

• The intel 4004 microprocessor was first microprocessor
• It was a 4-bit microprocessor
• Maximum clock frequency of Intel 4004 is 108khz to 740khz
• It is a 16 pin DIP (Dual In Package) IC
• It has 12-bit address lines
• It has register set contained 16 registers of 4-bit