8257 DMA CONROLLER

• The Intel 8257 is a programmable, 4-channel DMA controller (DMAC)
• 4 peripherals can request data transfer simultanously
• It is a 40-pin DIP IC

PINOUT DIAGRAM OF 8255 PPI

Intel 8255 (or i8255) Programmable Peripheral Interface

• The Intel 8255 is an intelligent programmable peripheral interface (PPI)ii
• It is a multiport input/output device
• It is a general purpose device for interfacing parallel I/O device to microprocessor/microcontroller bus
• Some manufactures use the term 'peripheral interface adapter'
• The main function of 8255 PPI ae to interface peripheral devices to microcomputer system
• It is a 40-pin DIP IC
• It operated on a single +5v dc supply
• It gas three 8-bit I/O ports, namely, Port A, Port B, & Port C
• Port C is further divided into two 4-bit ports-Port C upper & Port C lower
• Total 4-Ports are available, two 8-bit ports & two 4-bit Ports 
• Each port can be programmed as an input port or an output port 
• It has an 8-bit internal register to store the control word. the control word is used to configure the three ports of 8255 either as input or as output

FEATURES OF MICROCONTOLLERS

• As all the peripherals are integrated into a single chip, the overall system cost is very low
• The product is of a small size as compared to the microprocessor based systems and is thus very handy
• The system design requires very little efforts and is easy to trouble shoot and maintain 
• As the peripheral are integrated with a mp, the system is more reliable
• Though a microcontroller have on-chip RAM,ROM & I/O ports, additional RAM,ROM,I/O ports may be interfaced externally if required
• The microcontrollers with on-chip ROM provides a software security feature which is not available with microprocessor based systems using ROM/EPROM
• All these features are available in a 40-pin packages as in 8-bit processor

COMPLEX INSTRUCTION SET COMPUTER (CISC)

• A complex instruction set computer  is a computer where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions
• Generally, the instruction set of a CISC system is made efficient by incorporating a large number of powerful instructions
• Instructions are executed by micro-program
• Variable format instructions
• Supports complex addressing mode
• CISC systems have following drawbacks:

1. CPU COMPLEXITY : The control unit design (mainly instruction decoding) becomes complex since the instruction set is large with heavily encoded instructions
2. SYSTEM SIZE & COST: There is a lot of hardware circuitry due to complexity of the CPU. This increases the hardware cost of the system and also the power requirements
3. CLOCK SPEED: due to increase circuits the propagation delays are more and the CPU cycle time is large & hence the effective clock speed is reduced
4. RELIABILITY: The heavy hardware is prone to frequent failures
5. MAINTAINABILITY: Troubleshooting & detecting a fault is a big task since there are a large number of huge circuits. The invention  of microprogramming has reduced this burden to some extent. In built diagnostic microcodes were also provided in many CISC systems giving a helping hand to the hardware engineer in case of system failure.

INTEL 80486 (i486)

• The 80486 is the CPU with an on-chip floating point unit, introduced in 1989
• It is advanced, evolutionary high performance 32-bit microprocessor 
• It is fabricated using CHMOS -IV technology
•  It is a CISC (complex instruction set computer) processor
• It has 32-bit data bus
• It has 32-bit address bus
• It is available in 168-pin PGA (pin grid array) package
• It contains more than 1.2 million transistors 
• It is currently available with 25MHz , 33MHz, 50MHz, 66MHz & 100MHz clock
• It contains 8KB cache & an arithmetic coprocessor
• It executes many instructions in one clock period 

MEMORY ORGANISATION OF 8086

Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below).

16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte

32-bit addresses are stored in "segment:offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment:offset pair is calculated as:

address = (<segment> * 16) + <offset>

Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.

Data memory - the 8086 processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment).

Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations:0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment:offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address

FLAG REGISTER OF 8086

Flags is a 16-bit register containing 9 1-bit flags:

• Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand.
• Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented.
• Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
• Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
• Sign Flag (SF) - set if the most significant bit of the result is set.
• Zero Flag (ZF) - set if the result is zero.
• Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.
• Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.

ADDRESSING MODES OF 8086

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.

REGISTER ORGANISATION OF 8086

Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the 8086 microprocessor uses four segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions.

It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions.

Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

PINOUT DIAGRAM OF 8086

INTEL 80386

• The intel 80386 is the 1st 32-bit microprocessor introduced in 1985
• It is a logical extension of 8086 & 80286
• It has 32-bit data bus & 32 bit internal registers
• 32-bit ALU
• It is a 132 pin IC available in PGA (Pin Grid Array) package
• It uses a single +5v DC for the operation
• It has 32-bit non-muxed address bus
• It has break point registers
• It is capable of addressing 4 GB of Physical memory & 64 TB of virtual memory
• It is fabricated using CHMOS-III technology
• I contains 129 basic instructions
• It is software object code compatible with 8086 & 80286
• It contains 275,000 transistors on a single chip

INTEL 80286

• The intel 80286 microprocessor is an advanced version of the 8086 microprocessor that was designed , for multipurpose , multi-tasking,multi user enviroments in 1983
• The 80286 is a high performance, 16-bit microprocessor with on-chip memory protection & management capabilities
• It finds its applications in control systems as an embedded controller
• It is available in 68-pin PLCC (plastic lead chip carrier), 68-pin LCC(Leadless Chip Carrier)& 68-pin PGA (Pin Grid Array) packages
• It has 24 address lines
• It address 16 MB of physical memory  & 1GB of virtual memory
• The 80286 works in 2 operating modes - Real Address Mode (RAM) & protected virtual address made (PVAM). The operation of RAM is objected compatible & PVAM is source code compatible
• It is 6 times faster than the 8086
• The internal structure of 80286 contains 4 separate processing units. these are Bus Interface Unit (BIU), Instruction Unit (IU), Address Unit (AU) & Execution Unit (EU)
• The 80286 does not contains a muxed address/data bus
• I prevents the applications programs from performing I/O responding to interrupts & calling the system service directly excepted through pre-established entry points.

INTEL 8086

• Intel 8086 is a 1st member of 80x86 microprocessor family
• It is a 16-bit microprocessor
• It supports 16-bit ALU
• A set of 16-bit registers
• Most of the instructions are designed to work with 16-bit binary words
• It has 16-bit data bus
• It can be data from or write data into memory & ports either 8-bit or 16-bit at a time
• It has 20-bit address lines so it can address 2²⁰ =1,048,576 (1mb) memory locations
• It provide segment memory addressing capability
• A rich instruction set
• Powerful interrupt structure 
• 6 byte instruction queue
• Max clock frequency is 5,8,10MHz
• Memory divided into 2 banks (even & odd)
• Address range of memory is 00000-FFFFFH

PINOUT OF 8051

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to this pin, the program starts execution from the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output.

Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output.

Pin 12: INT0 Interrupt 0 input.

Pin 13: INT1 Interrupt 1 input.

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz.

Pin 20: GND Ground.

Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs.

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one additional (and cheap) integrated circuit. In other words, this port is used for both data and address transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists).

Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).

Pin 40: VCC +5V power supply.

INTEL 8051 MICRO-CONTROLLER

• The intel 8051 is an 8-bit micocontroller with 128 byte internal RAM & 4kb internal ROM.
• 8051 is a 40 pin DIP IC 
• It require +5v power supply
• max clock frequency rating is 12MHz
• It has 32 I/O ports & They are organised as 4 number of 8-bit parallel port
• It has harvard architecture in which the same address in different memory device or bank is used for program & data
• The architecture has two dedicated 16-bit pointers namely program counter (pc) & Data Pointer (DPTR)
• The PC is used as address pointer to access program instructions & it is automatically incremented after every byte of instruction fetch
• The DPTR is used as address pointer to read/write data in data memory & it is programmable using instructions 
• It has 16-bit address bus & 8-bit data bus
• They can address upto 64 k memory locations
• it supports 2 memory banks of 64kb each one for program & other for data
• It ha a separate 256 bytes internal RAM accessed by using 8-bit address 

MICRO CONTROLLER

• The micro-controller similar to microprocessors, But they are designed to work as a true single chip system by integrating all the devices needed for a system on a chip
• The basic functional units of a mp will be ALU, a set of registers,timing & control unit. the basic micro-controller will have these functional blocks & in addition may have I/O ports,programmable timer,RAM memory & EPROM/EEPROM memory
• The micro-controller is concerned with rapid movement of code & data within microcontroller: hence it has few instruction for data transfer between external memory & micro-controller
• The mc often manipulate with bits & so has large number of bit manipulating instruction 
• The mc can be used to form a single chip microcomputer based system without any additional ICs
• MC are used for designing application specific dedicated systems

ADSP 21XXX SHARC

• High performance superharvard architecture
• 32-bit processor
• It can execute every instruction in a single cycle
• Fast,flexible arithmetical computation units
• Dual address generators
• Efficient program sequencing
• It has 10-port data register file
• The ADSP 21000 family processors have 2 data address generators
• Architectural features supporting high level languages and operating systems 
• support IEEE 1149,IJTAG serial scan path & on-chip emulation features
• General purpose data & address register file
• Large address space 
• Pre & post modify addressing
• Onchip program , loop & interrupt stacks   

TMS 320C4X DIGITAL SIGNAL PROCESSOR

• Highest performance floating point digital signal processor
• It has 6 communication ports
• 6 channel DMA coprocessor
• Single cycle 40-bit floating point,32-bit integer multiplier
• 40 bit reegisters,8 auxiliary registers
• 14 control registers
• 2 timers
• 5v operation
• Separate internal program,data & DMA coprocessor buses for support of massive concurrent input/output of program and data through put, maximizing sustained cpu performance
• The c4x cpu has a register based architecture